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[VHDL-FPGA-Verilog] VHDL-Clock

Description: 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Platform: | Size: 4096 | Author: 单单 | Hits:

[VHDL-FPGA-Verilog] clock_CPLD

Description: 采用MaxPlusII写的一个小时钟程序，也是供初学参考。呵呵。注///版主，开发环境里面没有MaxPlusII.-MaxPlusII used to write a small clock procedures, as well as reference for beginners. Ha ha. Note///moderator, development environment there's no MaxPlusII.
Platform: | Size: 812032 | Author: Backy | Hits:

[VHDL-FPGA-Verilog] numberword

Description: 计数器控制程序，希望能够给大家帮助！文件在ＭＡＸ　ＰＬＵＳ下开发，调试通过-counter control procedures, we hope to be able to help! MAX PLUS document under development, through debugging
Platform: | Size: 1024 | Author: 吴军 | Hits:

[VHDL-FPGA-Verilog] electric_bell

Description: 电子打铃器 在max plus 2 下编译通过-electronic bell playing for the max plus 2 under through compiler
Platform: | Size: 13312 | Author: wenquan | Hits:

[Windows Develop] trafficontrol

Description: 使用verilog编写的交通灯控制程序，各方向通行时间可调，绿灯5s闪烁，在maxplus下调试通过，附仿真波形，在EP系列实验板上测试成功-use Verilog prepared by the traffic lights control procedures, the passage of time adjustable direction, green 5s flickered in maxplus under debugging, simulation waveforms with the EP series of successful experiments board test
Platform: | Size: 113664 | Author: 礼拜 | Hits:

[Other] cpusourcecodeusingmaxplus

Description: 一个用max+plus II写的很小的源码。简单但对初学还行吧-max plus one with a small II was the source. Simple but for beginners it is also OK
Platform: | Size: 1024 | Author: 风 | Hits:

[MiddleWare] pwm_VerilogHDLV1.1

Description: 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX　ＰＬＵＳ　ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
Platform: | Size: 232448 | Author: wjz | Hits:

[Other] MAXPLUS

Description: maxplus很好的学习书籍.详细介绍了maxplus操作流程及步骤,对学习maxplus很有帮助-maxplus good learning books. Details on the maxplus operating processes and steps, helpful to learn maxplus
Platform: | Size: 410624 | Author: Cory | Hits:

[Documents] 040207

Description: 数字钟电路系统由主体电路和扩展电路两大部分组成。其中，主体电路完成数字钟的基本功能，扩展电路完成数字钟的扩展功能。用MAXPLUSⅡ进行电路设计与仿真.-digital clock circuit system from the main circuit and the circuit extended two major components. Among them, the main circuit digital clock to complete the basic functions, expanding digital clock circuit to complete the expansion function. II FPGA used for circuit design and simulation.
Platform: | Size: 455680 | Author: 李明 | Hits:

[VHDL-FPGA-Verilog] CPLDxiaoche

Description: 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Platform: | Size: 1024 | Author: lili | Hits:

[Applications] C_10

Description: VHDL实例,在MAX+Plus+II下开发-VHDL example, the MAX II Plus under development
Platform: | Size: 1280000 | Author: 孙庆波 | Hits:

[Software Engineering] maxplus2shizishizhong

Description: 数字电子钟的设计 （二十四小时六十分钟六十秒）-digital electronic clock design (24 hours 60 minutes 60 seconds)
Platform: | Size: 500736 | Author: yan | Hits:

[VHDL-FPGA-Verilog] CHENGFAQI

Description: 本源码是高速并行乘法器的设计源码，开发软件为MAX+PLUS.输入为两个带符号的二进制数-the source is a high-speed parallel multiplier design source, development of software for MAX PLUS. with the importation of two symbols of binary-
Platform: | Size: 1024 | Author: 朱冬梅 | Hits:

[Windows Develop] cpu-maxplus

Description: MaxplusII编写的简易cpu，可实现简单加减法等操作-MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc
Platform: | Size: 513024 | Author: godtroop | Hits:

[Other] MaxPlusII

Description: Designing with MAX+PLUS -Designing with MAX+ PLUS
Platform: | Size: 905216 | Author: 陈宏 | Hits:

[Software Engineering] EDA234

Description: 文中给出了使用maxplus的完全手册同时也给出了maxplus的一些深入的介绍-In this paper, the use of the complete manual maxplus also gives some depth maxplus Introduction
Platform: | Size: 1801216 | Author: qibinchuan | Hits:

[VHDL-FPGA-Verilog] Electronwatch

Description: This a vhdl programme for realise an electron watch by max-plus II. The function includes time showing and time setting. It may be extended to other functions like alarming clock and so forth.
Platform: | Size: 1024 | Author: 施红希 | Hits:

[VHDL-FPGA-Verilog] SystemOfTaxiFeeBasedOnVerilogHDL

Description: 摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。 关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ-Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ
Platform: | Size: 211968 | Author: 杨轶帆 | Hits:

[Other] f_add

Description: 本文件包是在MAX+plus II 软件环境下实现半加器的逻辑功能-This document packet was MAX+ Plus II software environment to achieve a half-adder logic function
Platform: | Size: 12288 | Author: 罗理平 | Hits:

[Other] h_adder

Description: 本文件包是在MAX+plus II 软件环境下实现全加器的逻辑功能-This document packet was MAX+ Plus II software environment to achieve full adder logic function
Platform: | Size: 13312 | Author: 罗理平 | Hits:
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